In recent years. the development of semiconductor devices in which numerous elements are integrated on a chip. The development of a high density memory cell is being carried out. Particularly, a Dynamic Random Access Memories (DRAM) has been remarkably developed in terms of packing density. The DRAM is widely used in computer technology. Typically, the DRAM cells are applied to store data for a computer. These semiconductor memory devices have large capacitance for reading out and storing of information. Dynamic Random Access Memories are so named because their cells can retain information only temporarily, even with power continuously applied. The cells must therefore be read and refreshed at periodic intervals. An integrated circuit DRAM device typically has many memory cells. Indeed, a memory cell is provided for each bit stored by the DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor's channel and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. The formation of a DRAM memory cell includes the formation of a transistor, a capacitor and contacts to external circuits.
In order to achieve high density DRAM devices, the memory cells must be scaled down in size to the submicrometer range. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. In this case, because the area of the charge storage capacitor is also decreased, the capacitance becomes relatively small. This decrease in storage capacitance leads to lower signal-to-noise ratios and increase errors due to alpha particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often. A simple stacked planar capacitor generally cannot provide sufficient capacitance for good performance, even with high performance dielectric, such as Ta.sub.2 O.sub.5.
Prior art approaches to overcome these problems have resulted in the development of the trench capacitor. The process that made the trench capacitor is anisotropic etching of a silicon substrate. In the conventional trench capacitor cell the plate electrode of the storage capacitor is inside the trench, and the storage electrode is in the substrate. A dielectric film is formed over the surface of the electrode. The upper electrode of the capacitor is a polysilicon layer extending into the trench. Thus, the capacitor for the memory cell is formed.
One of the prior arts related to the trench capacitor can be seen in U.S. Pat. No. 5,374,580. Further, other approach can also be seen, for example "Trench Storage Node Technology for Gigabit DRAM Generations, K. P. Muller at el, 1996 IEEE, IEDM 96-507". Please see "A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al, 1993 IEEE, IEDM 93-627" and "SCALABILITY OF A TRENCH CAPACITOR CELL FOR 64 MBIT DRAM, B. W. Shen et al, 1989 IEEE, IEDM 89-27".
In addition, the silicon dioxide that is formed by using liquid phase deposition (LPD-oxide) exhibits good selective deposition and good flow characteristic. Thus, the LPD-oxide is an excellent trench-filling material. The basic reaction associated with the deposition of the LPD-oxide involves the action of the Si--OH. The dehydration reaction between the siloxane oligomers and Si--OH can be referenced to "A Selective SiO2 Film-Formation Technology Using Liquid-Phase Deposition for Fully Planarized Multilevel Interconnections, Tetsuya, Homma et al, J. Electrochem Soc., Vol. 140 No. 8, August 1993, The Electrochemical Society, Inc.". The chemical reactions for the LPD-oxide have been proposed by Nagayma as the following formulas: EQU H.sub.2 SiF.sub.6 +2H.sub.2 O=6HF+SiO.sub.2 .dwnarw. EQU H.sub.3 BO.sub.3 +4HF=BF.sub.4.sup.- +H.sub.3 O+2H.sub.2 O